The present invention relates voltage regulators and, more particularly, to the control of an in-rush current into a voltage regulator circuit.
Low drop-out regulators provide a minimum voltage drop between an input terminal and an output terminal while maintaining good regulation characteristics.
FIG. 1 is a circuit diagram illustrating an example of a low drop-out voltage regulator 10. An input voltage VIN is supplied to an input terminal 12 of the voltage regulator 10, where an input capacitor 13 having input capacitance CIN is provided at input terminal 12 in order to reduce the effects of a start-up surge current. Voltage regulator 10 produces an output voltage VOUT at an output terminal 14 by passing current from input terminal 12 to output terminal 14 through a pass transistor 40. An error amplifier 26 receives the output voltage VOUT through a divider network composed of resistors 44 and 46 and compares it to a reference voltage Vref from a reference voltage source 22. A control signal is produced at the output of error amplifier 20 that is coupled to input terminal 12 via resistor 34 in series with capacitor 36 and through capacitor 32, which form a compensation network for stability of the regulator 10. The control signal is then buffered by amplifier/driver 30 and the buffered signal drives the gate of pass transistor 40.
In regulator 10, pass transistor 40 is a PMOS (P-channel Metal Oxide Semiconductor) device and is typically a large-area power transistor configured to handle relatively large amplitude current. Typically, the pass transistor 40, as a MOS transistor, does not have a saturation voltage as is known with respect to bipolar transistors. Also, no base current is applied to the gate of pass transistor 40. There is a trend in current designs for voltage regulators to minimize the input to output voltage drop experienced from input terminal 12 to output terminal 14 and to maximize the current capability of the regulator. For example, with current designs, a drop-out voltage of 100 mV for a output current of 150 mA is typical.
Furthermore, an output capacitance (Cout), e.g. in the form of output capacitor 48, is typically required to provide for amplifier stability for a low drop-out voltage regulator. The output capacitor also improves the Power Supply Rejection Ratio (PSRR) characteristic for high frequencies above the amplifier""s bandwidth.
There is also a trend in current designs to reduce the regulator""s start-up time, e.g. the time required for the voltage regulator to achieve its steady operating state. Reduction of start-up time is typically achieved by allowing the MOS pass transistor 40 to deliver a large start-up current (or surge current) when the circuit is first enabled or switched on. The current required to obtain a start-up time of xcex94t seconds is described by the following equation:   I  =            C      out        ⁢          (                                    V            out                    ⁢                      (            nominal            )                                    Δ          ⁢                      xe2x80x83                    ⁢          t                    )      
In this equation, the current I is expressed in terms of the output capacitance Cout of capacitor 48 multiplied by the nominal output voltage at terminal 14 divided by the start-up time xcex94t. It is not uncommon to see a low drop-out voltage regulator designed to operate at 150 mA have a start-up or surge current on the order of 700 mA.
Although the start-up time for the voltage regulator may be reduced by increasing the start-up current, the high series resistance that is typical of batteries will result in a significant voltage drop in VIN at input terminal 12 when the high surge currents occur at start-up. Furthermore, these high voltage spikes at input terminal 12 can cause faulty circuit behavior. For example, a 3 V/10 mA battery application with a 700 mA start-up current can easily cause a 1.5 V voltage drop, depending upon on the capacitance CIN of the input capacitor 13. It is also common to observe oscillations at start-up due to the surge currents present at input terminal 12 if VIN drops below VOUT due to the effect of the surge current and the series resistance of a battery supply.
An embodiment of a control circuit for controlling an in-rush current of a voltage regulator circuit having a pass transistor, where the pass transistor has a control terminal, a first current terminal that is coupled to an input terminal of the regulator circuit, and a second current terminal coupled to an output terminal of the regulator circuit, where the control circuit includes a sense transistor having first and second current terminals and a control terminal, and where the first current terminal of the sense transistor is coupled to the input terminal of the regulator circuit and the control terminal of the sense transistor is coupled to the control terminal of the pass transistor. A ramp voltage generator circuit is provided for generating a ramp voltage signal responsive to a control signal received at an input terminal of the ramp voltage generator circuit. The control circuit includes a first current source having first and second current terminals and a control terminal, the first current terminal of the first current source being coupled to the input terminal of the voltage regulator circuit and the second current terminal of the first current source being coupled to the control terminal of the pass transistor. The control circuit also includes an amplifier having first and second input terminals and an output terminal, where the first input terminal of the amplifier is configured to receive a first voltage signal derived from the sense current, the second input terminal of the amplifier is configured to receive the ramp voltage signal, and the output terminal of the amplifier being coupled to the control terminal of the first current source. In a further refinement of this embodiment the first current source further comprises a current mirror circuit configured to operate from a low power supply voltage. In still another refinement of this embodiment, the control circuit further includes a limiting circuit having first and second current terminals, first and second input terminals, and an output terminal, the first current terminal of the limiting circuit being coupled to the control terminal of the current source, the second current terminal of the limiting circuit being coupled to the power supply terminal, the first input terminal of the limiting circuit being configured to receive a second voltage signal derived from the sense current, the second input terminal of the limiting circuit being configured to receive a predetermined threshold voltage, and the output terminal of the limiting circuit being coupled to the control terminal of the first current source, where the limiting circuit is configured to compare the second voltage signal derived from the sense current to the predetermined threshold voltage and generate a current limiting signal at the output terminal of the limiting circuit.
An embodiment of a method, according to the present invention, for controlling an in-rush current through a pass transistor of a voltage regulator circuit, calls for providing a sense transistor that mirrors the pass transistor, converting a sense current of the sense transistor into a first voltage signal, and generating a ramp voltage signal responsive to a control signal. The method then calls for comparing the first voltage signal to the ramp voltage signal to generate an in-rush current control signal and sourcing current to control terminals of the sense transistor and the pass transistor under control of the in-rush current control signal. In a further refinement of this embodiment of the present invention, the step of converting a sense current of the sense transistor into a first voltage signal includes converting the sense current of the sense transistor into a second voltage signal. This further refinement then calls for limiting the in-rush current control signal when the second voltage signal reaches a predetermined threshold.